The invention relates to a semiconductor device which includes an electrical component that is packaged in such a manner that electrical connections are made via terminal posts which are comprised of substrate material and which are provided with a conductive layer. The invention also relates to a method for making the semiconductor device.
With increasing high-scale integration in information technology, the demands with respect to assembly and interconnection technology by means of designs which are volume-saving and weight-saving are becoming ever more sophisticated. In many applications, it is only through the design of complex systems comprising highly integrated electrical components with a great number of external connections that the use of electronics becomes possible. Circuit boards are still the conventional system carriers.
Several years ago, a method of packaging electrical components was developed under the name of `chip size packaging` (referred to as CSP in the text that follows), wherein the space requirement of the packaged chip is no larger than 1.2 times the surface of the unpackaged component (Crowley et al., Workshop on Flip Chip and Ball Grid Arrays, Nov. 13-15, 1995, Berlin). An additional factor in the mounting of packaged components on circuit boards is that good connections must be ensured even for small dimensions. The method can be used for individual components, integrated circuits (IC's) as well as for high-frequency components.
A decisive factor is that a plurality of the components (in a wafer array) fabricated on a large-surface substrate can be processed by means of the process steps that are customary in semiconductor technology. This is an important prerequisite for low production costs while accomplishing high yields at the same time.
It is known that packaging according to the CSP principle is applied on the wafer level. The patents U.S. Pat. No. 5,403,729 and U.S. Pat. No. 5,441,898 describe such methods. They are comprised of a process sequence wherein an integrated circuit on the top side of a semiconductor material is covered with an insulating layer and electrical leads are placed from the IC to the substrate material by opening contact holes, with the leads having enlarged connecting areas at their ends. The substrate material residing between the connection points on the substrate and the IC is removed through trench etching. The entire surface is then covered with a further insulating layer which also fills the trench. A further etching takes place from the rear around the connection point that is predetermined on the front side, so that a terminal post is produced from the substrate material, which terminal post is electrically insulated from the remaining package and which projects slightly from the underside of the component. A metal layer on the underside of the post and on the side surface connects the front side contact electrically. The underside of the post serves as a contact surface when the electrical component is mounted on conductor tracks. Patent application AZ 197 06 811, which was not prepublished, describes a CSP fabrication method which increases the packaging density and, in the process, improves the adhesion of the terminal post to a conductor track. The `ball grid array` technique (BGA) is also part of the state of the technology, wherein the packaged component projects only slightly beyond the original chip surface (Y. Tomita, Studies of high pin count molded chip scale package, Area Array Packaging Technologies--Workshop on Flip Chip and Ball Grid Arrays). The special feature of the BGA method lies in the two-dimensional arrangement of the electrical connections within the chip surface.
A major drawback of this method is the additional surface requirement for the scribe lines beyond which the electrical contacts are guided as well as the limitation to peripheral connections. With increasing packaging density, the terminal posts may also end up too close to the component, in which case soldering may cause a short circuit.
Further drawbacks result from the comparatively long conductor tracks, which are guided beyond the chip edge, and the ensuing parasitic effects which have a disadvantageous effect especially for high-frequency applications.